UCIe-Based Chip-to-Chip Interconnect Verification

1 Challenge

Verify two generations of a chip-to-chip interconnect: an AXI adapter layer in Gen 1, then four 112G lanes with switchable Tx/Rx splits and multiple FLIT modes in Gen 2.

2 Approach

Designed custom AXI master and slave VIPs to drive AXI traffic, and enhanced the UVM testbench for each generation's design changes and new operating modes.

3 Outcome

Both generations delivered successfully. Gen 1 took 5 to 6 months, and Gen 2 took about three months. 112G is the highest lane rate in our delivered record.

4 Technical Scope

• Gen 1: 112G x 3, 312.5 Gbps aggregate with AXI adapter layer
• Gen 2: 4 x 112G with switchable Tx/Rx splits (Tx3/Rx1 for writes, Tx1/Rx3 for reads, Tx1/Rx1 for low power)
• Specialized FLIT modes optimized for latency and bandwidth
• Custom AXI master and slave verification IP (VIP)

5 Engagement Facts