Delivered Engagements

Case Studies: High-Speed Verification in Production

Seven delivered engagements across high-speed Ethernet, UALink, and UCIe-based die-to-die and chip-to-chip interconnect. Customer names are withheld; the industry, technical parameters, team sizes, and delivery timelines are described instead.

Ethernet Verification

400G Ethernet MAC/PCS in Four Configurations

Verified 400G Ethernet MAC/PCS across four configurations differing in lane count, lane rate, and channelization, including a 4 x 400G subsystem sharing 16 SerDes lanes for a global cloud services provider.

Team Size 2 to 4 engineers
Duration 1 to 2.5 mo / config
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Ethernet Verification

800G Ethernet MAC/PCS

Complete verification of a single-channel 800G Ethernet MAC/PCS scaling down to 100G over eight SerDes lanes for an AI inference chip startup. Delivered from start to sign-off in 2.5 months.

Team Size 4 engineers
Duration 2.5 months
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Ethernet Verification

400G and 50G Ethernet MAC/PCS Down to 10M

Multi-channel Ethernet verification across rate ranges from 400G down to 10M for three networking and data-center semiconductor customers. Successfully resumed and completed paused customer programs.

Team Size 4 to 6 engineers
Channels Up to 8 channels
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UALink

UALink 400G IP

Verification of UPLI, Transaction Layer, and Data Link layer plus end-to-end multi-channel operation across three port configurations for an AI accelerator chip company. Full UVM environment built from scratch.

Team Size 6 engineers
Duration 6 months
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Die-to-Die

UCIe-Based Die-to-Die Interconnect

Clean-slate verification of a custom UCIe-based die-to-die interconnect at 400G aggregate (56G x 8 lanes). SNOVA developed both the UVM testbench and a remote link-partner VIP for a semiconductor manufacturer.

Team Size 6 to 7 engineers
Duration 8 to 9 months
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Chip-to-Chip

UCIe-Based Chip-to-Chip Interconnect

Verification of two generations of high-speed interconnect: 312.5 Gbps aggregate with AXI adapter in Gen 1, and 4 x 112G lanes with switchable Tx/Rx splits and latency/bandwidth FLIT modes in Gen 2.

Lane Rate 112G (Highest in record)
Team Size 6 to 7 engineers
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FEC

FireCode FEC Soft Core for FPGA

Verification of a standalone FireCode FEC module soft core and custom design of a SerDes-side bit-slip gearbox for a semiconductor tooling vendor. Delivered in four weeks by two engineers.

Team Size 2 engineers
Duration 4 weeks
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