Case Study 4 | UALink & Scale-Up Fabric

UALink 400G IP Verification

Customer AI Accelerator Chip Co.
Max Rate 400G
Team Size 6 engineers
Duration 6 months

1 Challenge

Verify the UPLI, Transaction Layer and Data Link layer, plus end-to-end operation, across three port configurations. The DL environment needed restructuring and the other layer testbenches did not exist.

2 Approach

Refactored the DL environment and built the UPLI, TL and end-to-end environments from scratch, all fully UVM-based. Releases were staged: PCS only, then PCS and DL, then the full data path.

3 Outcome

Complete in six months, with the verification team scaling smoothly from three to six engineers after the first month to accelerate execution.

4 Technical Scope

  • 400G x 1, 200G x 2, 100G x 4 port configurations
  • 4 SerDes lanes at 100G, 4 channels
  • Block-level verification on UPLI, Transaction Layer (TL), and Data Link (DL) layer
  • End-to-end testing across the full protocol stack
  • 400G PCS verified as a separate project (1 engineer)

5 Engagement Facts

Customer Profile: AI accelerator chip company
Resource Allocation: 6 engineers (scaled from 3)
Timeline: 6 months staged delivery

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