Case Study 5 | UCIe & Chiplets
UCIe-Based Die-to-Die Interconnect Verification
Customer
Semiconductor Mfr.
Aggregate Bandwidth
400G
Team Size
6 to 7 engineers
Duration
8 to 9 months
1 Challenge
A clean-slate custom die-to-die interconnect based on UCIe at 400G aggregate, with no existing verification infrastructure.
2 Approach
While a separate customer design team implemented the RTL, SNOVA built the UVM testbench from scratch along with a custom UVM VIP acting as the remote link partner.
3 Outcome
Complete testbench environment and remote link-partner VIP delivered over 8 to 9 months, achieving functional coverage closure.
4 Technical Scope
- Custom UCIe-based die-to-die interconnect
- 400G aggregate bandwidth
- 56G x 8 lanes configuration
- UVM testbench built from scratch
- UVM remote link-partner VIP development
5 Engagement Facts
Customer Profile: Semiconductor manufacturer
Resource Allocation: 6 to 7 engineers
Timeline: 8 to 9 months
Resource Allocation: 6 to 7 engineers
Timeline: 8 to 9 months