Case Study 7 | FEC & FPGA Design
FireCode FEC Soft Core for FPGA
Customer
Semiconductor Tooling Vendor
Scope
FEC + Gearbox Design
Team Size
2 engineers
Duration
4 weeks
1 Challenge
Verify a standalone FireCode FEC module intended to run on an FPGA as a soft core, and provide a SerDes-side gearbox capable of bit-slipping.
2 Approach
Verified the core using pre-built FC-FEC UVM libraries with a UVM environment built from scratch, and custom designed the bit-slip gearbox RTL.
3 Outcome
Verification and bit-slip gearbox design delivered in four weeks by two engineers.
4 Technical Scope
- Standalone FC-FEC module implemented as an FPGA soft core
- UVM environment built from scratch
- Pre-built FC-FEC UVM verification libraries
- SerDes gearbox RTL design with bit-slipping capability
5 Engagement Facts
Customer Profile: Semiconductor tooling vendor
Resource Allocation: 2 engineers
Timeline: 4 weeks delivered
Resource Allocation: 2 engineers
Timeline: 4 weeks delivered